CPEN 202:Digital Systems Design (Prerequisite: CPEN 203)

Introduction to VHDL: overview of VHDL and characteristics, user interface and features, assignment statements, signal assignment, conditional signal assignment, statement generation, concurrent and sequential assignment statement, process statement, case statement, VHDL operator. Digital Systems Design: hierarchy and modular design of digital systems, design principles, functional units and building blocks and components, control concepts, timing concepts. Programmable devices: PLD, FPGA, PLA, ROM, PAL, CPLD. Modeling and Simulation: block diagram development, hierarchical schematic modeling, digital system modeling with VHDL, functional simulation of combinational and sequential circuits, flip-flop selection, timing models of digital circuit elements, timing simulation to measure delays, simulation and testing of circuit. Formal Verification: relationship between good design practice and formal verification, verification by model checking, verification by proof, verification by equivalence checking, verification by simulation, verification by testing, economics of verification, other verification – signal integrity, specification, reliability, safety, power, cooling. Fault models and testing of logic circuits: types and characteristics of common faults in digital circuits, single and multiple faults, test coverage, fault equivalence and dominance, fault simulation and grading, test generation algorithms, test generation algorithm for sequential circuits, memory testing and PLA testing.